Table 5-4. DMA States
Data Strobed Brief Functional
by
PCSS- DESCRIPTION
FB
1 1 1 1 101 1
Load upper DMA address latch
FD
l l l l l l01
Load mid DMA address latch
FE
1 1 1 1 1 1 10
Load low DMA address latch: start DMA
on rising edge of
LDO; block mode XFER
F7
11 11 11 11
Open path to int. DMA FlFO
(64
bytes)
EF
1 1 10 1 1 1 1
Read internal DMA status
DB7
=
1
if
no DMA or DMA cycle complete
DB6=
1
if
byte avail. from or to FlFO
DB5
=
1
if no FlFO overflow or underflow
9F
1001 11 11
Force IREQ- to high impedance
BF
10 1 1 1 1 1
1
Command complete signal to host
DF
1 101 1 1
1 1
Set DMA into a single word transfer
7F
01 11 1 11 1
Reset DMA and clear FlFO followed by FF
FF
1 11 1 1 11 1
to ensure proper DMA reset.
Data Valid
PCSD- (WF)
Load Upper
DMA
The LD2 output of the DMA chip is set low on the rising edge of
Address Counter
(FB)
PCSS- and then set high on the falling edge of PCSD-. This loads the
RIW-
and the umer
7
address lines A23-A17 from the data bus into
a counter on
the'
rising edge of LD2. This
8
bit counter need not be
reloaded if
its
contents are to remain unaltered in the succeeding op-
erations.
Load Mid
DMA
Address
Address lines A1 6-A9 are loaded into another counter in the same
Counter
(FD)
manner as above by the rising edge of LD1. This
8
bit counter also
need not be reloaded if
its
contents are to remain unaltered in the
succeeding operations.
Load
Low
DMA
Address
On the falling edge of PCSD-, LDO is set high to load the address lines
Counter
(FE)
A8-Al. The rising edge of LDO will start the DMA circuit. This also
implies a block mode transfer operation, since bits
7-4
are all high.
On power-up the DMA controller defaults to the block transfer
mode.
It
should be noted that all three address counters mentioned
above are cascaded allowing for the continues transfer of up to
64
Kbytes.
To Next Page
Loading...
