Command Complete
This will cause the assertion of the host vectored interrupt line to
its
Acknowledge
(BF)
active low state to indicate the completion of a command by the
HDC.
Word Transfer
(DF)
This will set the internal
DMA
circuit into a single word tranfer. On
completion of the word transfer, the
DMA
resets to a block transfer
mode. Hence this state must be strobed for every word transfer de-
sired.
Reset
DMA
(7F)
This state, followed by state 'FF', resets the
DMA
circuits and clears
the FIFO. This state should be strobed on power-up and to clear any
FIFO underflow or overflow conditions.
HOSTIHDC
COMMAND
Commands are passed to the HDC through the
DMA
circuit. When
PROTOCOL
the host requires a disk transfer a command block will be setup in
the 68000 memory followed by the host asserting the IREQ- line
low. The
280 will then go through a sequence for each lREQ as dis-
cussed below:
Step
1
:
Setting Up The
State FB is loaded into the
DMA
circuit with PCSS- followed by
DMA
Address
PCSD- with the hex value of desired high ordered address.
Bit
7
of
the data bus determines the direction of the transfer, a low will
cause a write operation to host and a high will cause a read from
host.
Then state FD is loaded into the
DMA
circuit with PCSS followed by
PCSD- with the value of desired address on the data bus. This sets up
address lines A1 6-A9.
State
DE
is loaded with PCSS- for a word transfer.
A
value of
06
is
loaded with PCSD- to point to the 12th and 13th bytes of the com-
mand block. On the falling edge of PCSD- the
DMA
word cycle will
begin. Byte 12 must be FF before the command is executed.
Step
2:
Reading Data
The state EF is loaded with PCSS- so that on the falling edge of
PCSD- internal
DMA
status will be outputed. The data lines DATA7,
DATA6, and DATA5 are examined until they are high indicating com-
pletion of the
DMA
cycle and that data has shifted through the FIFO.
For a block write operation to the disk, DATA6 is examined until low.
The HDC will sample the status for about 20
mS, until the data bus
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