Section
6
Fat
Agnus
Chip
DESCRIPTION
This specification describes the Fat Agnus chip, an N-channel HMOS
DMA
Controller. This IC device is able to produce. in a
68000
micro-
processor environment.
DMA
addresses by using a
RAM
Address
Generator and a Register Address Encoder. This device contains 25
DMA channel controllers, including the Blitter, Bitplanes, Copper,
Audio, Sprites. Disk and Memory refresh.
The
IC accepts a 28.63636 MHz crystal clock for the purpose of
generating
7.1
6
MHz and 3.58 MHz system clocks, dynamic RAM in-
terface for addressing up to 1 megabyte of memory and NTSC video
synchronization pulses.
Refer to Figure 6.1 for pin configuration, Figure 6.2 for
IC block dia-
gram and Table 6-1 for pin description.
This
IC device is equivalent to an
8370.
Warning
Improved versions of the Amiga custom chips are under devel-
opment. These chips are intended to be software compatible
with the existing chips. Writing incorrect values to reserved
bits, accessing undefined register addresses, reading write-only
registers or excessive cleverness may lead to compatibility
problems.
To Next Page
Loading...
