RAM
and
Register
Addressing
REGISTER
DESCRIPTION
The device generates
RAM
addresses from two sources, the proces-
sor or from the device performing
DMA
cycles selected by a multi-
plexer. This multiplexer allows the processor to access
RAM
when
AS* and RAMEN* are both low.
At
this time, the device also multi-
plexes the processor address (A1 -A1
8)
onto the
MA
bus. The device
places
A1 to
A8
&
A1
7
on the
MAO
to MA9 outputs, respectively,
during the row address time and places
A9
to A1
6
&
A1
8
on the
MAO
to MA9, respectively, during the column address time. The A1
9
line is used by the IC to determine which RAS line is to be asserted. If
A1 9 is low, RASO* is enabled, and
if
high, RASl* is enabled. The de-
vice also senses the LDS* and UDS* inputs to determine which CAS
to drop. If LDS* is low, the
IC will drop CASL*; if UDS* is low, CASU*
is dropped.
When the device needs to do a
DMA
cycle, the multiplexer disables
the processor from accessing
RAM
by asserting the Data Bus Re-
quest line (DBR*).
At
this time, the device multiplexes
its
generated
RAM
address onto the
MA
lines and will only make RASO*
90
low,
unless
it
is a refresh cycle where RASl* will also go low. During a
DMA
cycle, the IC device also asserts both CASU* and CASL*, unless
it
is a refresh cycle where they both remain inactive.
The device also generates
RGA
addresses from either the processor
or device
DMAs,
each of which is selected by another internal multi-
plexer. This multiplexer allows the processor to perform a register
readlwrite access when AS* and RGEN* are both low. The device
then takes the low order byte of the processor address
A1 to
A8
and
reflects
its
value on the
RGA
output bus RGAl to RGA8. The device
will reflect the status of PRW input on the RRW output line, to indi-
cate a memory read or write operation.
During a device
DMA
cycle, the multiplexer prevents the processor
from doing a register access by asserting the
DBR*
line. The device
then places the contents of
its
register address encoder onto the
RGA bus.
This
DMA
controller device contains
97
registers that can be ac-
cessed after the following conditions have been met: the state of AS*
and RGEN* must be an active low level and the least
8
significant ad-
dress bits
(A1 thru
A8)
must contain the valid address of the register
to be accessed.
The following is a detailed description of the register set.
REGISTER FUNCTION
AUD
X
LCH
Audio channel
X
location (high
3
bits)
AUD
X
LCL
Audio channel
X
location (low
15
bits)
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