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Commodore Plus 4 - Page 309

Commodore Plus 4
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Using
Interrupts
on
the
Plus/4
297
The
address
of
the
data
is
found
by
adding
the
index
to
the
base
address.
An
instruction
in
indirect
indexed
mode
consists
of
2
bytes.
The
first
is
the
opcode
for
the
desired
instruction.
The
second
is
the
low
byte
of
the
location
at
which
the
base
address
is
found.
The
high
byte
of
the
location
at
which
the
base
address
is
found
is
assumed
to
be
zero
and
is
not
specified.
In
the
machine-language
monitor,
an
indirect
indexed
mode
instruction
appears
in
this
form:
mnemonic
($hli),Y
where
mnemonic
is
an
instruction
mnemonic,
h
represents
a
hexadecimal
digit,
and
$hh
is
the
zero
page
location
of
the
low
byte
of
the
base
address.
The
zero
page
location
following
the
specified
zero
page
location
must
contain
the
high
byte
of
the
base
address.
The
following
instructions
are
available
in
indirect
indexed
mode:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC,
and
STA.
Indexed
Indirect
Mode
In
this
mode
the
X
register
is
used
as
the
index.
The
zero
page
base
address
is
specified
with
the
instruction.
The
address
of
the
data
is
found
at
the
address
created
by
adding
the
index
to
the
base
address.
An
instruction
in
indexed
indirect
mode
consists
of
2
bytes.
The
first
is
the
opcode
for
the
desired
instruction.
The
second
is
the
low
byte
of
the
base
address.
The
high
byte
of
the
base
address
is
assumed
to
be
zero
and
is
not
specified.
In
the
machine-language
monitor,
an
indexed
indirect
mode
instruction
appears
in
this
form:
mnemonic
($hli,X)
where
mnemonic
is
an
instruction
mnemonic,
h
represents
a
hexadecimal
digit,
and
$hh
is
the
zero
page
base
address.
The
value
of
the
index
is
added
to
the
base
address.
The
location
thus
pointed
to
must
contain
the
low
byte
of
the
address
of
the
data;
the
following
location
must
contain
the
high
byte
of
the
address
of
the
data.
The
following
instructions
are
available
in
indexed
indirect
mode:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC,
and
STA.
Using
Interrupts
on
the
Plus/4
When
a
task
such
as
the
incrementing
of
a
real-time
clock
must
be
performed
on
a
regular
basis,
it
is
frequently
impractical
to
use
straight-line
code.
To
alleviate
this
problem,
the
6502
is
equipped
with
processor
interrupt
capability.
The
Plus/4
implementation
of
interrupts
is
described
in
this
section.
The
6502
has
an
IRQ
(interrupt)
line.
When
this
line
is
activated
by
an

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