Commodore Plus 4 - Page 310

298 Machine Language on the Commodore Plus/4
interrupt, the processor performs a number of tasks. First, the current instruction
is completed. Next, the program counter and processor status register are pushed
onto the stack. Program control is then transferred through the IRQ vector at
$FFFE-$FFFF to an interrupt service routine.
The IRQ vector at $FFFE-$FFFF is located in the operating system ROM. It
points to a routine in the operating system ROM that initiates interrupt process
ing. First, all three user registers are pushed onto the stack (accumulator, then X
register, then Y register). Then it checks for the BRK instruction (B) flag in the
saved processor status register. Finding that the interrupt was not caused by a
BRK instruction, a jump indirect is performed through a vector at $0314-$0315.
This is normally the location of programmer intervention. To have a special
function performed, this vector can be changed to point at a user routine. To
complete the interrupt processing, either jump to the normal operating system
routine (the address of which can be found in $0314-$0315 on power-up), or pull
all three registers and return as shown here:
PLA
TAY
PLA
TAX
PLA
RTI
The RTI instruction restores the processor status register and program counter
from the stack. Hence, all of the processor registers are returned to their preinter-
rupt state, and the main program continues executing.
The SEI instruction can be used to disable interrupts. This sets the I bit in the
processor status register. While this bit is set, the processor cannot be interrupted
by a maskable (and non-BRK instruction) interrupt. The CLI instruction is used
to reenable interrupts.
The Plus/4 is equipped with an interrupt enable register ($FF0A). Setting the
appropriate bit in this register will cause the corresponding interrupt to occur
(when the I bit is clear). The Plus/4 also has an interrupt status register ($FF09).
The high bit of this register is set to 1 when an interrupt occurs. The remaining bits
are set to 1 when the corresponding device has an interrupt condition. These bits
are set regardless of the interrupt enable status of the device and therefore can be
used for timing or other functions with or without actually interrupting the
processor. All of the bits in this register are cleared to 0 by writing a 1 to them. The
bit corresponding to a device interrupting the processor must be cleared before it
can interrupt again.