CTX CMS-3435 - Deflection Circuitry

Each three color signal pairs are then mixed
together by Q406, Q407, Q410, Q411, Q414 and
Q415 to be RGB signals with analog values. The
level of these signals is also controlled by
Q403 for users to set contrast. Finally these
signals are output to the video preamplifier 1C501
through buffers Q408, Q412 and Q416. -
1C501(M51387) is a video processing iC
equipped with three DC amplifiers to preamplify
RGB signals from 0.6V to 2V. The voltage gain
of these amplifiers is all DC controlled, so simple
voltage divider with resistors and trimmers can
be used to adjust the voltage gain of each RGB
signal’s amplification and thus achieve a well
balanced white picture. Clamping circuit is also
included in this IC to obtain a constant black level
on the amplified video output signals.
Let us take Red signal channel for instance, and
the same principle applies on both Green and
Blue signal channels. The input signal is AC
coupled through C501 to Pin 3 of IC501, the
voltage setting on Pin 4 of IC501 determines the
voltage gain of the Red Preamplifier, this voltage
is controlled by VR501 together with R504 and
R505. VR501 is thus designated R Subcontrast
adjustment which is to be adjusted together with
the other two Subcontrast adjustments to
achieve a well balanced white picture.
Clamping pulse to Pin 15 of 1C501 is taken from
Pin 12 of 1C803(74LS123) to trigger the internal
DC Restoration circuit in order to obtain a cons-
tant black level of the Red video signal output
from Pin 29 of IC501. Now this Red signal output
is ready to drive video output stage located on
CRT board.
Voltage setting on Pin 14 of IC501 further deter-
mines the voltage gain for all three channels and
can be used as user contrast control. An ACL
(Automatic Contrast Limit) circuit is equipped in
this monitor to prevent the CRT from being over-
driven. When anode current grows larger than
the limiting threshold, the voltage on Pin 14 will
drop and decrease the gain to force the video
signal output from 1C501 smaller and the anode
current is limited within 350uA for long term ope-
ration.
The video output stage contains three identical
cascode amplifiers to amplify the video signals
from 1C501 to the level of 45Vp-p capable of
driving CRT. These large signals are AC coupled
to the CRT cathods, and the Brightness control
circuit introduces a DC voltage onto each cathod
for CRT cut-off and Brightness control.
11
3. Deflection Circuit
3.1 Sync Processing Circuit
The sync processing circuit can handle both TTL
level separate or composite sync of any polarity
and composite sync on Green Video of negative
polarity. For TTL sync, the horizontal sync is
sent to Pin 2 of IC404(74LS136), then processed
by Q421, Q423 and XOR gate of IC404 to get a
positive sync pulse on Pin 6 of IC404 in spite of
the polarity of input sync. For composite sync
on Green Video, signal is sent to peak detector
Q418, the detected sync tip is then amplified by
Q419, Q420 and shaped by XOR gate to get also
a positive sync pulse on Pin 11 of 1C404. The
monitor can not synchronize with two sync sig-
nals at the same time, so Q422 serves as a switch
to turn off the detected composite sync pulse
whenever there is a TTL horizontal sync
detected. The positive sync pulse is then
processed by Q424, Q301 and sent to Pin 1 of
1C301(LA7850) for sychronization.
For TTL separate vertical sync, it is sent to Pin
10 of 1C404 and output from Pin 8 of |C404, but
if the vertical sync is in composite form, then it is
filtered out by R469, C419, R470, C420 from the
sync pulse detected on Q424, and sent to Pin 9
of 1C404, also output from Pin 8 of IC404 to be
further processed.
3.2 Frequency Voltage Conversion Circuit
The horizontal sync pulse from Q301 is also sent
to Pin 7 of frequency voltage converter IC302
(IR9331) to be converted into a DC voltage which
is proportional to the sync frequency. This vol-
tage is compared with the reference voltage by
the comparator circuit to identify the horizontal
frequency and make necessary changes of the
parameters in the deflection circuit.
The voltage output of the horizontal frequency
voltage conversion circuit has an upper limit
about 14V set by R342, R343 and D306, also a
lower limit about 5.5V set by D307 and IC301 (OP
Amp.). These limits ensure that the monitor will
not go out of the specified scanning range and
cause any damage of the output stage.
The vertical sync pulse from Pin 8 of |C-404 is first
processed by 1C405 to obtain uniform polarity
pulse in spite of input sync polarity change. It is
then sent to both 10301 (LA7850) for sychroniza-
tion and 1C202(HA17555) for frequency voltage
conversion. The converted DC voltage is used
to determine whether input frequency is higher
than 80H, if it is, then the vertical deflection pa-
rameters are preset to conform with IBM 8514A
graphic standard which uses 87Hz for vertical
interlaced scanning frequency.