Cypress Semiconductor CY7C68013A - Page 48

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 48 of 62
10.13 Slave FIFO Output Enable
Figure 25. Slave FIFO Output Enable Timing Diagram
[20]
10.14 Slave FIFO Address to Flags/Data
Figure 26. Slave FIFO Address to Flags/Data Timing Diagram
[20]
Table 29. Slave FIFO Output Enable Parameters
Parameter Description Min Max Unit
t
OEon
SLOE Assert to FIFO DATA Output 10.5 ns
t
OEoff
SLOE Deassert to FIFO DATA Hold 10.5 ns
SLOE
DATA
t
OEon
t
OEoff
Table 30. Slave FIFO Address to Flags/Data Parameters
Parameter Description Min Max Unit
t
XFLG
FIFOADR[1:0] to FLAGS Output Propagation Delay 10.7 ns
t
XFD
FIFOADR[1:0] to FIFODATA Output Propagation Delay 14.3 ns
FIFOADR [1.0]
DATA
t
XFLG
t
XFD
FLAGS
NN+1
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