DATA PRECISION 938 User Manual

42-5124 MODEL 938
the FET Q4 is turned ON during 4>3 to connect the stored charge
in the unknown capacitance to the discharge circuit.
For measurement of higher capacitances, the <i>3 signal turns ON
04 and then 06, so that the discharge now takes place through
R16 and/or R1 1. ( Note that the measurement of voltage through
R11 is, effectively a 4-wire connection.) Changes in range scale
for the higher ranges is now accomplished by changing the
number of repetition cycles for each of the charge/discharge ac 
tions averaged. This is accomplished by switching connections
to the timing logic element, Z5.
4.3.2 Measuring the Change in Charge
In each $1 interval, the capacitor reaches some nominal charged
value (not necessarily the applied voltage), and the exact value is
not critical to the accuracy of measurement. In each *3 interval
the discharging capacitor generates a current in the range-
selected resistance paralleling and charging C3. Over a number
of such cycles, C3 stores a voltage proportional to the average
value of the current generated by the discharging capacitor.
4.3.3 Measuring the Difference in Voltage
The non-inverting input to Z1-1 is always connected to the high
side of the input connector, and to the unknown capacitor. The
operational amplifier drives a FET follower to develop a current
in the output resistor divider load so that the voltage across R4,
R5, and R6 in series is equal to the charge on the capacitor.
(The output “ follows ” the input capacitor voltage.) When the <i>2
control signal is active, the scaled output (at the voltage divider
junction of R5 and R6) appears across C4 and 05 in series.
When the 4>4 control signal is active, the scaled output appears
across C4 only. Since the value across 04 and 05 at <i>2 is the
value before discharge, and the value across 04 at 4>4 is the
value after discharge, then the value remaining on 05 is the dif 
ference.
4.3.4 Zero Adjustment
Transistor Q7, R7 and R8 provide a path for current flow from the
REFERENCE of the A/D converter to the input. The current in this
path is controlled by the value of the voltage at the non-inverting
input to Z1. Current will flow through this circuit until the
voltage developed across the two resistances R7 and R8 equals
that input voltage. Thus, a current proportional to the reference
is drawn from the discharge current. That current is calibrated
by adjustment of R8. It remains a constant count, even though
each measuring operation with difference capacitors develops
different INPUT and REFERENCE voltages.
4-8
MODEL 938 PRINCIPLES OF OPERATION
Figure 4-6. Signal Conditioning Waveforms (Z5)
4.4 SIGNAL CONDITIONING CONTROL LOGIC
Control signals for the signal conditioning circuits are developed in
Z5. The input to Z5 is the output from a master oscillator, crystal-
controlled to generate 32.768 KHz. It is counted down to develop
timing waveforms depending upon the switch-selected jumpering
shown in the reference schematic, and illustrated in Figure 4-6.
4.5 A/D CONVERTER DETAILS
4.5.1 Analog Section.
The Model 938 A/D Converter is a monolithic CMOS chip contain 
ing both analog and digital sections on the same chip. Figure
4-7- illustrates the analog section, and includes the interfaces
with discrete elements on the main pc-board. As shown in the il 
lustration, the converter consists of a buffer, integrator, and
comparator, configured by internal switches programmed by the
digital section. The switches are identified by the names of the
step intervals during which they are “ on ” . For example, the iNT
switches are closed during Step 2, Integration of the Conditioned
Input; The A/Z switches are closed during Step 1, the Autozeroing
step; the DE switches are closed during Step 3, Integration of the
Reference Voltage. Note that the DE switches are closed in
pairs: DE( + ) when a positive conditioned input is sensed at the
end of Step 1, and DE(-) when a negative conditioned input is
sensed at the end of Step 2.
(The steps of the A/D conversion are not synchronized with the
four phases of the signal conditioning described earlier.)
During Step 1 (Autozeroing; A/Z switches closed), the conditioned
input is removed (INT is open); the A/D input is shorted to Analog
Common, the integrator-comparator loop is closed, and capacitor
C9 is charged with compensating offset for the automatic zero 
ing during Steps 2 and 3 to follow. Capacitor C6 is charged with
the reference voltage for later use in Step 3.
4-9

DATA PRECISION 938 Specifications

General

Brand	DATA PRECISION
Model	938
Category	Measuring Instruments
Language	English