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DATA PRECISION 938 User Manual

DATA PRECISION 938
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42-5124
MODEL
938
4.2.2
The
Capacitor
initial
Charge
When
Switch
A
(Figure
4-4)
is
closed
during
4>1,
the
capacitor
under
test,
Cy
is
charged
rapidly
to
some
nominal
value,
limited
to
2.8
volts.
The
voltage
level
on
the
capacitor
is
connected
to
the
non
inverting
input
of
amplifier
Z1-1,
which
draws
no
current
(and
therefore
no
charge)
from
the
capacitor.
The
amplifier
output
drives
a
FET
follower
that
is
cut
off
during
4>3.
The
voltage
ap
pears
across
the
voltage
divider
R4,
R5,
and
R6
(of
which
R4
is
a
variable
resistance
with
which
to
adjust
the
gain
of
the
stage).
During
<i>2,
Switch
B
is
closed,
and
capacitors
C4
and
C5
in
series
are
charged
with
the
scaled
value
of
the
initial
Cy
voltage.
4.2.3
The
Capacitor
Discharge
Interval
During
<t>3,
Switch
C
is
closed
(Figure
4-4),
connecting
the
charg
ed
capacitor
to
the
range-selected
value
of
load
resistance
through
which
to
partially
discharge
the
capacitor.
During
repeated
cycles
of
this
phase,
the
filter
action
of
R9
and
C3
acts
as
an
averaging
operation,
storing
the
average
value
of
the
cur
rent
as
a
voltage
across
03.
This
value
is
connected
as
the
IN
PUT
to
the
A/D
converter.
4.2.4
The
Voltage
Change
Measurement
During
T4,
Switch
D
closes
(Figure
4-4),
connecting
the
scaled
output
from
amplifier
Z1-1
to
C4.
Since
C4
and
C5
in
series
had
previously
been
charged
with
the
initial
value
of
the
charged
capacitor,
capacitor
C5
now
retains
the
value
of
the
difference
between
the
two
samplings.
This
becomes
the
input
to
the
REFERENCE
terminals
of
the
A/D
converter.
4.2.5
Zero
Adjustment
Adjustment
to
zero
on
all
ranges
is
accomplished
by
subtracting
a
current
proportional
to
the
Reference
voltage
from
the
discharge
current
flowing
in
the
range-selected
load
resistance.
This
is
limited
to
±20pF.
4.2.6
Range
Scale
Selection
Range
scale
conditioning
of
the
two
signals
(difference
in
charge
and
difference
in
voltage)
is
accomplished
by
several
methods.
For
full
scale
values
of
200pF,
2nF,
20nF,
and
200nF,
the
resistance
divider
introduces
a
proportionate
load
for
the
discharge
cycle
of
the
capacitor,
and,
therefore,
a
proportionate
current
to
be
averaged
for
the
A/D
INPUT
signal.
For
the
higher
end
of
the
range
scales
(2uF,
20uF,
200uF,
and
2000uF),
the
charge-discharge
timing
cycle
is
changed
by
range-alteration
of
4-6
MODEL
938
PRINCIPLES
OFOPERATION
the
control
logic
timing
circuit.
The
interval
is
lengthened
by
fac
tors
of
10
to
obtain
a
greater
voltage
change
during
the
discharge
phase
for
large
value
capacitors.
4.2.6
Display
The
display
is
driven
directly
from
the
A/D
converter
integrated
circuit.
Each
of
the
three
full
digits
is
configured
by
a
combina
tion
of
1
to
7
segments,
each
driven
by
a
separate
line
from
the
A/D.
The
liquid
crystal
back
plane
is
driven
by
a
square
wave
signal,
and
the
appropriate
sgment
in
each
digit
is
driven
by
an
out-of-phase
component
at
the
same
frequency
as
the
back
plane.
A
single
line
from
the
A/D
drives
the
most
significant
digit
“
1
”
,
and
another
line
drives
the
polarity
sign
(not
used
in
the
C-Meter).
Range
selection
activates
Exclusive
OR
gates
for
the
decimal
point
drives;
the
other
input
to
each
gate
is
the
back
plane
drive
signal.
A
low
battery
sensing
circuit,
comparing
the
battery
(or
Batter
Eliminator)
output
with
an
internal
reference,
develops
a
drive
signal
for
the
LO
BAT
indicator
in
the
display.
Insertion
of
the
jack
for
the
Battery
Eliminator
removes
the
internal
battery
from
the
power
supply
circuit.
4.3
SIGNAL
CONDITIONING
DETAILS
4.3.1
Charging
and
Discharging
the
Capacitor
Refer
to
the
complete
schematic
at
the
back
of
this
manual.
Note
that
the
input
unknown
capacitance
is
paralleled
internally
with
a
capacitor
(C1)
which,
with
the
stray
capacitance
of
the
assembly,
always
provides
some
“
zero
”
capacitance
for
the
meter.
This
small
capacitance
always
charges
up
in
parallel
with
the
capacitance
under
test,
and
is
the
amount
that
is
zeroed
out
with
the
thumbwheel
adjustment
before
connecting
the
capacitor
to
be
measured.
The
capacitor
under
test
is
connected
to
the
HI
and
LO
terminals
(keeping
the
poarities
correct
for
polarized
components).
Q1
and
Q2
are
clamps,
keeping
the
voltage
at
safe
levels,
and
protecting
internal
components.
Q3
is
a
switching
transistor
that
is
turned
ON
during
<I>1
to
connect
the
rail
value
to
the
HI
terminal.
The
power
supply
circuit
described
later
keeps
the
voltage
to
be
developed
across
the
unknown
capacitance
to
a
safe
limit
of
2.8
volts
(nominal).
For
measurment
of
low
capacitance
values,
range
selection
of
100pF
to
100nF
opens
the
base
drive
to
transistor
Q6,
and
only
4-7

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DATA PRECISION 938 Specifications

General IconGeneral
BrandDATA PRECISION
Model938
CategoryMeasuring Instruments
LanguageEnglish