Datapulse 101 - Page 30

ADDENDA AND ERRATA
Datapulse Model 101 Pulse Generator
E. O.
NO.
EFFECTIVE
DATE
DWG. NO.
A
CHANGE
2021
2028
2081
8~26-66
6-9-66
8-26-66
Transistor
Equiv.
Manual
T rans istor
Substitution
SM 1330, P/N12685—004is an accept—
able substitute for DP63-6, P/N 22635—
006.
Section 1, paragraphs 1.7, 1.7.1,
1. 7.2 and 1. 9 should read as follows:
1.7 TRIGGER OUTPUTS
The trigger outputs are positive
with a duration of approximately 50
nanoseconds.
1.7.1 Advance Trigger
The advance trigger has an
amplitude of l. 7 volts from a 50 ohm
source impedance and is available on
internally triggered operations only.
It occurs approximately 10 percent of
the repetition rate period before the
reference trigger.
1.7.2 Reference Trigger
The reference trigger has an
amplitude
of
2.
0
volts
from
a
50
ohm
source and occurs approximately 30
nanoseconds
after
the
unit
is
triggered
from
an
external
source,
or
10
percent
of the repetition rate period after the
advance
trigger
on
internally
triggered
operations.
1. 9 PULSE DELAY
The pulse delay (with respect to
the reference trigger output) is contin—
uously
variable
by
means
of
a
six
position
decade
switch
and
a
fill—in
vernier
con-
trol
over
a
range
of
approximately
40
nanoseconds
to
10
milliseconds.
The
maximum
duty
cycle
is
at
least
70
per—
cent.
ZNZlOZ,
P/N
12686
may
be
used
in
lieu
of
ZNZZ70,
P/N
12695—001.