Datron 1062 - Page 32

24
3. 2. 3. 4
High Speed
Buffer
C22
slows the
switching
edges
from the multiplexer
M35 so
that the
buffer
cannot
slew-limit
and
thus
lose
the
charge. The
signals are
fed
to
Q36,
M34
which
comprise a
high
speed buffer with
high common mode
rejection
ratio (See
Fig. 3.16). The
common mode
rejection is
dependent
on the power
supplies
of
Q36
(from R66 and
R11-R15)
being
bootstrapped
to
the output
of the
buffer,
via D2
and
D4.
Thus
the
difference
between
input signal
and
power
supply around
the input
stage is
maintained
constant
whatever the
input signal.
3.2.3.5
Integrator
The
basic
Integrator
comprises R6, R7
and
C9,
with
hybrid amplifier Q35
and M25.
(See
Fig.
3.17).
Low-noise
FET-pair Q35
also has
low gate
leakage,
which
maintains
the
effectiveness
of
'sample-and-hold'
components R34
and C12.
An
inverted and attenuated
version of the
integrator
output
voltage is developed
across R5.
This is applied
via
R4 and
CIO to
compensate
for the
small amount of
dielectric
absorption
in
C9.
The
value of
R5
is factory-
selected to
equalize
readings
of
the
same
input, taken at
differing
read-rates
(including
'one-shot'
measurements).
C11
and
R27
provide
shorter term
compensation,
R23
being set to
correct
linearity at 10%
of full range.