Datron 1062 - Page 57

44
PROCESSOR
A2
ADDRESS
A1
BUS
A«2
IB
2B
3B
4B
SELECT
1Y
2Y
3Y 4Y
R/V
RAM
DO D1
02 D3
04 D5 D6 D7
—
1
j
—
t
h
h
}\ j }\ j
I
I
02
XDDSP
DO 01 02
03
04
05 06
07
PROCESSOR DATA BUS
FIG. 3.47
DISPLAY
DRIVER
WRITE
CIRCUITRY