Datron 1062 - Page 58

45
To Anode
Drive
Circuitry
(Display
Blocit
Select
I
To
Cathode
Drive
Circuitry
(Segment Select
I
FIG. 3.49
SIMPLIFIED
DISPLAY
DRIVER
READ
CIRCUITRY
3.10
DISPLAY
DRIVER
ASSEMBLY
(Circuit
Drawing
No.
430330).
Basically, the
Display
Driver
assembly
receives
the
display
information
from the
microprocessor
(running at
800kHz)
and stores
it
in
a
Random
Access
Memory
(RAM)
digit by
digit.
This data is
then
read
out at
a
slower
fre-
quency
(2kHz),
level
shifted
and output
to
the gas
discharge
display.
NOTE:
In
the
following
description,
each bar,
decimal
point or legend
is
referred
to as
a
display
segment
and
each set
of
segments
i.e.
+1,0
or a
legend block,
is
referred to as
a
display
block.
3.10.1
Write
Mode
On
completion
of a
reading
or
when
certain modes
are
selected, (e.g.
ERROR,
keyboard
entry),
the processor
indicates
to
the Display
Driver
Board that data
is ready to
be
transferred by
the
signal XDDSP
(TP6). This
causes
the
RAM (Ml)
to be
placed
into its
write mode
and the
quadruple
2-line to
1-line data
selector,
M9,
to
select
the
'B'
inputs
which are
connected to
the
processor
address
bus.
The
signal XDDSP
also
causes the
tri-state
buffers M6
and
M7 to
become
enabled,
causing the data
input
lines
of
the
RAM
to
be
connected to
the
processor data
bus.
Thus
under MPU
control,
the
display
data
(+1,
S
's,
decimal
points
and legends)
is
written into
the
RAM.
Once
this
transfer of
data
is
complete the
RAM be-
comes
deselected,
the
buffers
return to
their third
state
inhibiting
the data
bus to
the RAM
and
connects the
'A'
inputs
of
M9
to
the address
lines
of the
RAM.
3.10.2
Read Mode
Discharge
between
adjacent
display blocks
is
preven-
ted by
time
multiplexing
and
sending
information to
alter-
nate
blocks.
A particular
display
block
is
selected by
driving
its
anode,
and a
particular
segment by
driving
the
segment
cathode.
The
free running
clock M13, R3,
R5, C16,
produces a
2kHz signal (Ml
3-9) to
drive
a
4-bit
binary counter,
M8,
which
provides
the
control
of the
address
lines
in the
read
mode
(See
Fig. 3.49).
The
display
block
selection
is
achieved by
decoding
these
4 lines
into 16
bits
using
Mil.
The output
lines of
Mil are
connected to
the
bases
of
transistors
Q1-Q3,
Q13-Q20
which
act as
anode
switches.
Note
that
when
the
address
lines
are in
the state 0000
the
output
of
Mil
(pin
11)
selects
the
anode to
block
1,
0001
selects
the anode
to
block
3
(Ml 1-9),
0010 ...
block
5,
etc.,
thus
the
display
blocks
are
selected
alternately.
To
select
the
appropriate
segment
data
from
the
RAM to
match
the
display
block
selection the
address
lines
are
given
a
left hand
bit
rotation
i.e. if the
output of
M8
is
labelled DCBA,
(2^,
2^, 2
\
2°), the
address
input
of Ml
would
be CBAD.
(Fig. 3.48
gives
the
state
of
the
address
lines
for each
display
block).
The
particular
display
block
segment
data
is
recalled by
the
RAM,
buffered
by
M4
and
M5,
level shifted
-180
volts
by
R8-R15,
C4-C1
1
causing
Q5-Q12
to
drive the
cathodes, D1-D10
acting
as
restoration
diodes.
Between
the
transfer of each
set of
segment data.
Ml
3-1
3
is taken
high,
causing
the outputs
of
M4
and
M5
to
be a
logic
'O'.
This
produces a
refresh
period
for
capacitors
C4-C11 to
discharge
from the
-180V
supply
through
the
restoration
diodes.