DEC VT220 - Page 109

BLINK ATR H
ATR
I.ATCH
4
J
BOLD ATR H } ~~DEO
OUTPUT
REV/NORM
ULATR H TO
~C~I.K~C~L~Rr---- VIDEO
CONVERTER
(ALT SELl TO
.. CHAR
GEN
REV ATR H
BLINK ATR H
BOLD ATR H
NORM FiElD H
FROM
CPU
LOGIC
FROM
CHAR
GEN
FROM _--:.B_L_iN_'K_H __
DUART ~
\
ATR
LATCH
u.~ __ --t~3~~
FROM ,
TIMING i ---' I I
GEN \ T51. '-t---
FROM ~-!C-l-Ri---<------'---+i -+1------+1
BLANK jCBLANK L I -t
l
I
CIRCUiTS '8
CLR
r-." -.-.JI I
VLT H GATE Jl
FROM c~ < r - P-t>JUI. AiR H I
9007 S~~ H II -<1\-J i I
SC1H _ ~
Figure 6-21 Attribute Circuits Block Diagram
• CLR gate clears value stored in attribute latch 3
whenever the screen is being blanked (CBLANK L) and
active line time (VLT H) is not occuring.
• UL ATR gates -- gates underline attribute with scan line
address values input from the 9007 VPAC to define an
underline output only during the ninth and tenth scan
lines of the character being processed.
• Attribute latch 4 is the output stage of attribute
circuits, clocked on leading edge of T5 L to latch inputs
provided by attribute latch 3 and UL ATR gates, with the
reverse attribute input from attribute latch 3 exclusive
ORed with NORM FIELD H control input from the CPU logic.
Later in this chapter, Table 6-2 describes the signals shown in
Figure 6-21.
6-25