DEC VT220 - Page 116

Table 6-2
Video Logic Signal Descriptions
Mnemonic
A0--A3 H
A'~--A5 H
A0--A13 H
A00--A07 H
ALT SEL H
Signal
Address bits 0-3 high
Address bits 0-5 high
Address bits 0-13 high
Address/data bits 0-7
high
Alternate select high
6-32
Description
Input to address mux in
character generator
from CPU logic defining
scan line of alternate
character generator RAM
to be accessed for read
(RO L) or write (WR L)
transaction
Input to 9007 VPAC from
CPU logic defining
internal register to be
accessed (SEL CRT L)
for read or write
transaction (type of
transaction defined by
address)
Address outputs from
9007 VPAC during OMA
transactions defining
CPU logic RAM and
attribute RAM addresses
to be accessed for read
of character and
attribute data
Oata bus lines used to
transfer attribute data
from attribute RAM to
character generator
during OMA transactions
Select signal to
character generator ROM
(ALT SEL H low) and
alternate character
generator RAM (ALT SEL
H
high) developed by
character generator
access mux from either
CPU logic input (when
CPU is accessing
alternate character
generator RAM), or from
input defined by
attribute of character
being processed for
output