DEC VT220 - Page 117

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
ATR/CHR
BAD0--BAD7 H
BLINK H
BLINK ATR H
Signal
Attribute/c~aracter
Buffered data bits 0-7
high
Blink high
Blink attribute high
6-33
Description
Timing generator output
controlling transfer of
attribute (ATR/CHR low)
and character address
values (ATR/CHR high)
into line buffer RAM
(during DMA
transactions) or out of
line Buffer RAM to
attribute latch 2 and
character latch 2
(during active line
time)
Data bus used by CPU
logic to transfer data
to and from 9007 VPAC,
or to and from the
alternate character
generator RAM, and by
video logic to transfer
character address data
from the CPU logic RAM
to the character
generator circuit
DUART signal which
produces blink rate at
screen; BLINK H is
gated with blink
attribute (BLINK ATR H)
at attribute circuits
with BLINK H high for
blink off at screen and
low for blink on
Enables blinking
display at screen
through biasing of
video output stage
circuit (intensity of
video output increased
for BLINK ATR H high
and decreased for BLINK
ATR H low)