DEC VT220 - Page 118

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
BNKS0--BNKS1 H
BOLD H
CBLANK H
CBLANK L
CGBLANK H
CHR0--CHR7 H
Signal
Bank select 0-1 high
Bold high
Composite blank high
Composite blank low
Composite gated blank
high
Character bits 0-7 high
6-34
Description
DUART signals defining
the two most
significant bits of
line buffer RAM
address
Enables bold displ at
screen through biasing
of video output stage
circuit (intensity of
video output increased
for BOLD ATR H high and
decreased for BOLD ATR
H low)
CRT controller output
defining screen
blanking during
vertical and horizontal
retrace periods
Control defining screen
blanking developed from
either CBLANK H, during
retrace periods, or
from DIS VIDEO H,
during self-test
Gated from CBLANK Land
used as clock to cursor
skew PIP in video
output circuit to reset
double width control at
start of each
horizontal and vertical
retrace period
Parallel dot matrix
data output from
character generator to
video converter
defining dot pattern of
display characters on a
scan line-to-scan-line
basis