DEC VT220 - Page 119

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
CHR ADDR WR L
CHR LD L
CHRG SEL H
(CLEAR)
CRT CLK H
CSYNC L
Signal
Character address write
low
Character load low
Character generator
select high
(Clear)
CRT clock high
Composite sync low
6-35
Description
Input to access mux in
character generator
used to develop VIDEO
LATCH H when CPU is
supplying address value
to character generator
to be used to access
alternate character
generator RAM for
read/write transaction
Input to PIS converter
enabling load of
parallel character dot
matrix data (CHR0-CHR7
H)
Input to character
generator ROM providing
MSB of address, with
bit defining which
character set is to
accessed during
character processing
for screen display
(ASCII or DEC
multinational)
Output from blank
circuit (developed from
CBLANK L) to clear
input of PIS converter
and attribute latch 4
at start of each
retrace period
Timing generator clock
output to CRT
controller generated at
T5 time
CRT controller output
to video output circuit
to be gated with video
data to define vertical
and horizontal sync for
composite video output
to optional slave
monitor