DEC VT220 - Page 120

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
CURS H
Signal
Cursor high
Description
CRT controller output
used duri horizontal
retrace periods to
define a double width
data row to be
processed
DIS VIDEO H
Disable video high DUART si
generate
signals
self-test
nal us
blanking
i
t
DMA H
DMA REQ L
DOT CLK H
EN CHR GEN
RW H
EN CHR GEN L
DMA high
DMA request low
Dot clock high
Enable character
generator read/write
high
Enable character
generator low
6-36
Acknowl ement from
CPU relinquishing
control of AD0-7 Hand
BAD0- H data bus lines
to controller
for access 0 screen
characte address and
attribute values
Interr to CPU from
CRT controller
requesti CPU give up
data bu es for video
logic access of screen
character address and
attr values
Timi generator signal
prov ing sic timing
for video logic with
one active clock for
each dot of screen
displ
CPU logic signal to
access mux character
generator selecting for
CPU logic inputs during
CPU access of character
genenerator
CPU logic signal to
alternate character
generator RAM and
read/write buffer in
character generator
enabling CPU access for
read/write transactions