DEC VT220 - Page 121

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
HOR SYNC L
INH L
LBA CLK L
LBA CLKS H
LBA CLR L
LBA CLRS H
Signal
Horizontal sync low
Inhibit low
Line buffer address
clock low
Line buffer address
clocks high
Line buffer address
clear low
Line buffer address
clears high
6-37
Description
CRT controller output
defining horizontal
sync time
Control within video
converter conversion
control circuit which
prevents serial
shifting of dot matrix
display data during
double width row
processing
Clock input to line
buffer address counter
developed from either
LBA CLKS L (from CPU
logic) or T5 L (from
timing generator) by
character generator
access mux
Cleek input from CPU
logic to character
generator access mux
used to develop LBA CLK
L during CPU access of
character generator
Clear input to line
buffer address counter
developed from either
LBA CLRS L (from CPU
logic) or VLT L (from
CRT controller) by
character generator
access mux
Clear input from CPU
logic to character
generator access mux
used to develop LBA CLR
L during CPU access of
character generator