DEC VT220 - Page 122

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
LBF DISABLE H
LBF WR L
NORM FIELD H
RD L
RESET CRT L
RESET TIM L
REV ATTR H
Signal
Line buffer disable
high
Line buffer write low
Normal field high
Read low
Reset CRT controller
low
Reset timing generator
low
Reverse attribute bit
high
6-38
Description
Control input to
character generator
enabling character
address values being
presented to character
generator to be passed
to alternate character
generator RAM without
being inadvertently
written to line buffer
RAM
Timing generator output
enabling write of
character address and
attribute values into
line buffer RAM during
DMA transactions
Control input from CPU
logic defining dark
screen background
CPU logic input to
character generator
read/write buffer
defining direction of
data transfer between
CPU and alternate
character generator RAM
CPU logic signal
resetting CRT
controller to known
start state
CPU logic signal
resetting timing
generator to known
start state
Defines reverse display
at screen for character
being processed
(character dot matrix
"on" dots at same value
as screen background)