DEC VT220 - Page 123

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
(REV/NORM)
SC0-SC3 H
SEL
ATR0 L
SEL
ATRl L
SEL
CRT L
Signal
(Reverse/normal)
Scan address bits 0-3
high
Select attribute RAM 0
low
Select attribute RAM 1
low
Select CRT controller
low
6-39
Description
NORM FIELD H and REV
ATTR H exclusive ORed
and gated with SERIAL
DATA L for display "on"
for "on" dots (REV/NORM
high) when NORM FIELD
H/REV ATTR Hare
opposing states
(reverse on light
screen or normal on
dark), or for display
"on" for 1I 0 ff" dots
(REV/NORM low) when
NORM FIELD H/REV ATTR H
are identical states
(reverse on dark screen
or normal on light)
Address inputs to
character generator
address mux from CRT
controller defining
scan line of character
to be processed from
either character
generator ROM or
alternate character
generator RAM
Enable to attribute
RAM 0 when CPU logic is
accessing the RAM for a
write, or when being
accessed for DMA
transaction
Enable to attribute
RAM 1 when CPU logic is
accessing the RAM for a
write, or when being
accessed for DMA
transaction
Enable to CRT
controller when CPU is
accessing this device
for read/write
transaction