DEC VT220 - Page 124

Table 6-2
Mnemonic
(SERIAL
DATA L)
SYNC DMA H
Video Logic signal Descriptions (Cont)
Signal Description
(Serial data stream low) Bit stretched serial
dot matrix data output
from PIS converter to
video output defining
"on" and"off" bits of
display
Synchronized DMA high Timing generator output
developed from DMA H
synchronized to ATR/CHR
time
T1-T5 H,T2 L
T3 L, T5 L
TBLK L
TVB H
UL ATR H
VERT SYNC L
Timing signals 1-5 high,
2-3 and 5 low
Test blank low
Test video bits high
Underline attribute
high
Vertical sync low
6-40
Timing generator
clocking signals
outputs to video logic
circuits
Blank control to video
output circuit
developed from CBLANK L
(CBLANK L low for
either retrace periods,
from CBLANK H, or
during self-test, from
DIS VIDEO H), and
preventing video output
from turning display on
Status output to DUART
from video output
circuit used during
self-test to sample
condition of video data
stream
Enables generation of
underline at display by
being gated with SERIAL
DATA L to turn all dots
"on" during ninth and
tenth scan lines of a
processed character
CRT controller output
defining vertical sync
time