DEC VT220 - Page 125

Table 6-2
Video Logic Signal Descriptions (Cont)
Mnemonic
VIDEO LATCH H
VLT HIL
WR L
132 COL H
Signal
Video latch high
Visible line time
high low
Write low
132 column high
Description
Character generator
access mux output
enabling either CPU
access of alternate
character generator RAM
(VIDEO LATCH H
developed from CHR ADDR
L) or video logic
transfer of character
address and attribute
values to line buffer
RAM (VIDEO LATCH H
developed from T5 L)
Control outputs from
CRT controller defining
screen data processing
time (horizontal trace
periods)
CPU logic input to
alternate character
generator RAM enabling
CPU access for write
transaction when that
device is selected (EN
CHRGEN L)
Control input to timing
generator from DUART
defining number of
characters per screen
data row
6.4 SCHEMATIC REFERENCE INFORMATION
Table 6-3 identifies the logic board component coordinates and
schematic page and coordinate for each of the video logic
components and circuits identified in this chapter.
NOTE
The reference information provided in
Table 6-3 is based Rev. A of the logic
board schematics (CS 5415653-9-1).
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