EN25QH64A104HIP (DIGITAL_DSP : IC782)
Block diagram
DO (DQ
1
)
WP# (DQ
2
)
VSS
CS#
DI (DQ
0
)
CLK
HOLD#/RESET# (DQ
3
)
VCC
1
2
3
4
8
7
6
5
Serial Interface
X-Decoder
Address
Buffer
And
Latches
CS# CLK DI (DQ0) DO (DQ1)
HOLD# / RESET#
(DQ3)
WP# (DQ2)
Flash
Memory
Y-Decoder
I/O Buffers
and
Data Latches
Control Logic
Note:
1. DQ
0
and DQ
1
are used for Dual instructions.
2. DQ
~ DQ
are used for Quad instructions.
M12L64164A-5TG2Y (DIGITAL_DSP : IC784)
Block diagram
A3V64S40GTP
64M Single Data Rate Synchronous DRAM
Revision 1.0 Dec., 2012
CLK : Master Clock U,LDQM : Output Disable / Write Mask
CKE : Clock Enable A0-11 : Address Input
/CS : Chip Select BA0,1 : Bank Address
/RAS : Row Address Strobe Vdd : Power Supply
/CAS : Column Address Strobe VddQ : Power Supply for Output
/WE : Write Enable Vss : Ground
DQ0-15 : Data I/O VssQ : Ground for Output
PIN CONFIGURATION (TOP VIEW)
ESMT
M12L64164A (2Y)
Elite Semiconductor Memory Technology Inc. Publication Date: May 2012
Revision: 1.1 2/45
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11 Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
BA1 , BA0 Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE active.
L(U)DQM Data Input / Output Mask
Makes data output Hi-Z, t
SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC No Connection This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decoder
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Output
Buffer
Address
Clock
Generator
CLK
CKE
Command Decoder
CS
RAS
CAS
WE
Before Servicing
This Unit
Electrical Mechanical Repair Information Updating
51
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