Denon DN-C680 - Page 11

11
11DN-C680
XCS05XL-5VQ100C (MA: IC112)
XCS05XL-5VQ100C Terminal Function
Pin
No.
Port Name Symbol I/O Ext Note
1 GND GND - - GND(0V)
2 I/O,GCK1 I/O - - Not used. Open
3 I/O -PRST I Pd Reset signal 'L':Reset(internal register cleared)
4 I/O,TDI I/O - - Not used. Open
5 I/O,TCK I/O - - Not used. Open
6 I/O,TMS I/O - - Not used. Open
7 I/O -R I Pu Read signal
8 I/O -W I Pu Write signal
9 I/O -CS1 I Pu Chip select signal
10 I/O -CS2 I Pu Chip select signal
11 GND GND - - GND(0V)
12 VCC VCC - - Power supply(+3.3V)
13 I/O D0 I/O Pu Data bus
14 I/O D1 I/O Pu Data bus
15 I/O D2 I/O Pu Data bus
16 I/O D3 I/O Pu Data bus
17 I/O D4 I/O Pu Data bus
18 I/O D5 I/O Pu Data bus
19 I/O D6 I/O Pu Data bus
20 I/O D7 I/O Pu Data bus
21 I/O,GCK2 CHGOFT O - Off track detect sensitivity select signal
22 M1 M1 I - FPGA(XCS05XL) Mode select 'H':Slave serial mode
23 GND GND - - GND(0V)
24 M0 M0 I - FPGA(XCS05XL) Mode select 'H':Slave serial mode
25 VCC VCC - - Power supply(+3.3V)
26 -PWRDWN -PWRDWN I - FPGA(XCS05XL) control signal:Power down(Not used. Internal pullup)
27 I/O,GCK3 A20 I - Address bus
28 I/O(HDC) CHGICO O - RF equalizer specification select signal
29 I/O A21 I - Address bus
30 I/O(-LDC) I/O O Pu FPGA(XCS05XL) control signal:-LDC(Not used)
31 I/O PDI0 I Pu Parallel port 'L':Play command input
32 I/O PDI1 I Pu Parallel port 'L':Pause command input
33 I/O PDI2 I Pu Parallel port 'L':Standby/cue command input
34 I/O PDI3 I Pu Parallel port 'L':Track+ command input
35 I/O PDI4 I Pu Parallel port 'L':Track- command input
75
76
100
1
25
26
50
51