Denon HOME 350 - Page 38

CY8C4045AZI-S413 (IC8001)
Block Diagram
Peripherals
CPU Subsystem
System Interconnect (Single Layer AHB)
PSoC 4000S
Architecture
IOSS GPIO( 5x ports)
I/O Subsystem
Peripheral Interconnect (MMIO)PCLK
SWD/ TC
NVIC, IRQMUX
Cortex
M0+
48 MHz
FAST MUL
FLASH
32 KB
Read Accelerator
SPCIF
SRAM
4 KB
SRAM Controller
ROM
8 K B
ROM Controller
32-bit
AHB- Lite
2x SCB-I2C/SPI/UART
36x GPIOs, LCD
DeepSleep
Active/ Sleep
Power Modes
Digital DFT
Test
Analog DFT
System Resources
Lite
Power
Clock
Reset
Clock Control
IMO
Sleep Control
REFPOR
Reset Control
TestMode Entry
WIC
XRES
WDT
ILO
PWRSYS
5 x T C P WM
CapSense
WCO
2x LP Comparat or
High Speed I/ O Matrix & 2x Programmable I/ O
Before Servicing
This Unit
Electrical Mechanical Repair Information Updating
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