Need help?Do you have a question about the Epiq Solutions Sidekiq NV100 and is the answer not in the manual?
Introduces the hardware interfaces of the Sidekiq NV100.
Discusses how to use and integrate the Sidekiq NV100.
Explains the usage of the JTAG fixture for debugging.
Covers the Sidekiq NV100 NUC Platform Development Kit.
Provides a system-level block diagram of the platform.
Describes the externally accessible hardware ports.
Explains how to power the system up and down.
Details the M.2 form factor, RF transceiver range, and bandwidth.
Explains the various receive, transmit, and combined RF modes.
Details the specifications for the RF receiver.
Details the specifications for the RF transmitter.
Covers specifications for reference clocks and synchronization.
Lists M.2 slot type, FPGA, flash, GPS, sensors, and temperature ratings.
Describes the first U.FL antenna port and its RF mapping.
Describes the second U.FL antenna port and its RF mapping.
Details the U.FL connector for GPS antenna input.
Explains the function of the four status LEDs on the device.
Describes the W.FL connector for external PPS signal input.
Details the W.FL connector for external 10 or 40 MHz reference clock input.
Describes the W.FL connector for the 40 MHz reference clock output.
Explains the W.FL connector for accessing a single FPGA GPIO pin.
Discusses the RF shield's role in thermal management.
Covers on-board temperature and IMU sensors for orientation.
Provides a detailed pinout for the M.2 edge connector.
Covers host compatibility, BIOS, OS support, and FPGA reprogramming.
Discusses RF interfaces, system connection, and detection methods.
Lists power consumption figures under various operating conditions.
Discusses thermal dissipation and GPS module power estimates.
Covers selection between internal and external reference clocks.
Explains GPSDO functionality and its components.
Presents performance data for the GPSDO, including frequency error.
Details GPS sysfs entries and NMEA message output via UART.
Discusses limitations with host system sleep/hibernation modes.
Explains how to access JTAG signals via the M.2 connector.
Provides usage notes for the Sidekiq NV100 JTAG Fixture.
Guides the setup for the JTAG fixture using Thunderbolt3.
Introduces and guides the setup of the NUC PDK system.
Lists included applications like I/Q capture, ERA, and setup for JTAG/flash recovery.
Details the NUC's RF ports, GPIO connector, and JTAG connector.
General| Instantaneous Bandwidth | Up to 56 MHz |
|---|---|
| Transmitter Output Power | Up to 10 dBm |
| FPGA | Xilinx Artix-7 |
| Operating Temperature | -40°C to +85°C |
| Bandwidth | 56 MHz |
| Form Factor | mPCIe |
| Power Consumption | 3.5W (typical) |
| Interface | PCIe |
| Type | Software Defined Radio Transceiver |
| RF Frequency | 70 MHz to 6 GHz |
| ADC Resolution | 12 bits |
| Frequency Range | 70 MHz – 6 GHz |
To Next Page
