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Epiq Solutions Sidekiq Z2 Development Manual
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Sidekiq Z2 and Matchstiq Z3u FPGA
Development Manual
Version 3.16.2
Updated 03/10/22
2
Table of Contents
Table of Contents
5
About this Document
8
Legal Considerations
8
Proper Care and Handling
8
Introduction
9
References
10
Terms and Definitions
11
FPGA Reference Design
12
Overview
12
Top Level
13
Figure 1: Sidekiq Z2 Simplified Block Diagram
13
User_App
14
Figure 2: User App Block Diagram
14
User_App Signals
15
Rx Path Inputs to User_App
16
Outputs from User_App
17
Figure 3: Sample Timing Diagram
17
User_App Tx Interface
18
User_Reg_If
18
Figure 4: Sample User App to IIO Diagram
18
Reg_If / User_Reg_If
19
Iio_Data_If
20
Timestamp_Block
20
Gpio/Uart
21
System_Wrapper
22
Sidekiq Z2 System_Wrapper
22
Matchstiq Z3U System_Wrapper
22
Figure 5: Sidekiq Z2 Zynq Processing System
25
Building and Debugging
26
Building a User_App
26
Sidekiq Z2 Reference Design
26
Matchstiq Z3U Reference Design
26
Custom User_Apps
27
Building the Project and Bitstream
27
Build with Linux
28
Building Sidekiq Z2
28
Building Matchstiq Z3U
28
Build with Windows
29
Programming
29
Programming the Sidekiq Z2 FPGA
29
Programming the Matchstiq Z3U FPGA
29
Testing the Bitstream
29
Using JTAG for Debug
29
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Hardware User Manual
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Getting Started Guide
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Epiq Solutions Sidekiq Z2 Specifications
General
Brand
Epiq Solutions
Model
Sidekiq Z2
Category
Network Hardware
Language
English
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