Epson S1C6200A - Page 24

18 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
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XH, i
XL, i
YH, i
YL, i
r, i
r, q
A, Mn
B, Mn
Mn, A
Mn, B
MX, i
r, q
MY, i
r, q
MX, e
F, i
F, i
SP
SP
r
XP
XH
XL
YP
YH
YL
F
r
XP
XH
XL
YP
CP
LD
LDPX
LDPY
LBPX
SET
RST
SCF
RCF
SZF
RZF
SDF
RDF
EI
DI
INC
DEC
PUSH
POP
Index
operation
instructions
Data
transfer
instructions
Flag
operation
instructions
Stack
operation
instructions
Classification Operand
IDZC
↑
↓
↑
↓
↑
↑
↑
↑
↑
↓
↑
↓
↑
↑
↑
↑
↑
↓
↑
↓
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Clock
Operation Code Flag
XH-i3~i0
XL-i3~i0
YH-i3~i0
YL-i3~i0
r
← i3~i0
r
← q
A
← M(n3~n0)
B
← M(n3~n0)
M(n3~n0)
← A
M(n3~n0)
← B
M(X)
← i3~i0, X ← X+1
r
← q, X ← X+1
M(Y)
← i3~i0, Y ← Y+1
r
← q, Y ← Y+1
M(X)
← e3~e0, M(X+1) ← e7~e4, X ← X+2
F
← FVi3~i0
F
← FΛi3~i0
C
← 1
C
← 0
Z
← 1
Z
← 0
D
← 1 (Decimal Adjuster ON)
D
← 0 (Decimal Adjuster OFF)
I
← 1 (Enables Interrupt)
I
← 0 (Disables Interrupt)
SP
← SP+1
SP
← SP-1
SP
← SP-1, M(SP) ← r
SP
← SP-1, M(SP) ← XP
SP
← SP-1, M(SP) ← XH
SP
← SP-1, M(SP) ← XL
SP
← SP-1, M(SP) ← YP
SP
← SP-1, M(SP) ← YH
SP
← SP-1, M(SP) ← YL
SP
← SP-1, M(SP) ← F
r
← M(SP), SP ← SP+1
XP
← M(SP), SP ← SP+1
XH
← M(SP), SP ← SP+1
XL
← M(SP), SP ← SP+1
YP
← M(SP), SP ← SP+1
Mne-
monic
Operation
↓
↓
↓
↓
↑
↓
↑
↓
↓
↓
↓
↓