Epson S1C6200A - Page 51

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 45
3 INSTRUCTION SET
JP NZ,s Jump if not zero
JP NZ,s
PCB ← NBP, PCP ← NPP, PCS ← s
7 to s0 if Z = 0
0111s
7 s6 s5 s4 s3 s2 s1 s0 700H to 7FFH
I
5
Not affected
Not affected
Not affected
Not affected
Jumps to the destination address specified by the 8-bit operand when the zero flag
is not set.
JP NZ,10H
PCB 1 1
NBP 1 1
PCP 0000 0000
NPP 0000 0000
PCS 0000 0111 0001 0000
Z flag 0 0
JP s Jump
JP s
PCB ← NBP, PCP ← NPP, PCS ← s
7 to s0
0000s7 s6 s5 s4 s3 s2 s1 s0 000H to 0FFH
I
5
Not affected
Not affected
Not affected
Not affected
Unconditional jump to the destination address specified by the 8-bit operand.
PSET 0AH JP 10H
PCB 0 0 0
NBP 0 0 0
PCP 0000 0000 1010
NPP 0001 1010 1010
PCS 0100 0010 0100 0011 0001 0000