Epson S1C6200A - Page 66

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
60 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD YL,r Load r-register into YL
LD YL,r
YL ← r
1110100110r1 r0 E98H to E9BH
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the four low-order bits of register Y.
LD YL,B LD YL,MX
YL register 1011 1010 0111
B register 1010 1010 1010
Memory (MX) 0111 0111 0111
LD YP,r Load r-register into YP
LD YP,r
YP ← r
1110100100r1 r0 E90H to E93H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the 4-bit page part of index register IY.
LD YP,MX LD YP,A
YP register 0011 0000 0100
A register 0100 0100 0100
Memory (MX) 0000 0000 0000