Epson S1C6200A - Page 68

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
62 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
NOT r NOT r-register (one's complement)
NOT r
r ← r
110100r1 r0 1 1 1 1 D0FH to D3FH
II
7
Not affected
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Performs a one's complement operation on the contents of the r-register.
NOT A NOT MY
A register 1001 0110 0110
Memory (MY) 1111 1111 0000
Z flag 0 0 1
OR r,i Logical OR immediate data i with r-register
OR r,i
r ← r ∨ i
3 to i0
110011r1 r0 i3 i2 i1 i0 CC0H to CFFH
II
7
Not affected
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Performs a logical OR operation between immediate data i and the contents of the
r-register. The result is stored in the r-register.
OR B,5 OR MX,0BH
B register 0100 0101 0101
Memory (MX) 0011 0011 0111
Z flag 0 0 0