Epson S1C6200A - Page 70

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
64 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
POP r Pop stack data into r-register
POP r
r ← M(SP), SP ← SP + 1
11111101 0 0r1 r0 FD0H to FD3H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into the r-register. SP is incremented by 1.
POP B
SP C0 C1
Memory (C0H) 1001 1001
B register 0101 1001
POP XH Pop stack data into XH
POP XH
XH ← M(SP), SP ← SP + 1
11111101 0 101 FD5H
VI
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into XH, the four high-order bits of X. SP is incremented by 1.
POP XH
SP CE CF
Memory (CEH) 0110 0110
XH register 0010 0110
2
3
2
2
2
1
2
0
M(SP) =
= r-register
2
0
2
1
2
2
2
3
2
3
2
2
2
1
2
0
M(SP) =
= XH
2
0
2
1
2
2
2
3