Epson S1C6200A - Page 73

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 67
3 INSTRUCTION SET
POP YP Pop stack data into YP
POP YP
YP ← M(SP), SP ← SP + 1
11111101 0 111 FD7H
VI
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into YP, the 4-bit page part of IY. SP is incremented by 1.
POP YP
SP C0 C1
Memory (C0H) 0000 0000
YP register 0001 0000
PSET p Page set
PSET p
NBP ← p
4, NPP ← p3 to p0
1110010p4 p3 p2 p1 p0 E40H to E5FH
III
5
Not affected
Not affected
Not affected
Not affected
Loads the most-significant bit of the 5-bit immediate data p to the new bank
pointer (NBP) and the four low-order bits to the new page pointer (NPP).
PSET 1FH JP 00H
PCB 0 0 1
NBP 0 1 1
PCP 1000 1000 1111
NPP 0001 1111 1111
PCS 0010 0011 0010 0100 0000 0000
2
3
2
2
2
1
2
0
M(SP) =
= YP
2
0
2
1
2
2
2
3