Epson S1C6200A - Page 8

2 EPSON S1C6200/6200A CORE CPU MANUAL
1 DESCRIPTION
Fig. 1.1 Block diagram
I DZC
ALU
S1C6200 CORE CPU
4-bit address bus
8-bit address bus13-bit address bus
4-bit data bus
12-bit data bus
Stack Pointer (8)
XHL (8)
YHL (8)
RP (4)
Program Counter Block
Micro-Instructions
Instruction Decorder
Instruction Register (12)
Program Memory
ROM
(8,192 12-bit words max.)
Data Memory
RAM, Peripheral I/O
(4,096 4-bit words max.)
A (4)
TEMPB (5)
B (4)
TEMPA (5)
Interrupt
Controller
Timing
Generator
Oscillator
XP (4)
YP (4)