Epson S1C6200A - Page 82

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
76 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
RZF Reset zero flag
RZF
Z ← 0
11110101 1 101 F5DH
VI
7
Not affected
Reset
Not affected
Not affected
Resets the Z (zero) flag.
ADD A,3 RZF
Z flag 0 1 0
A register 1101 0000 0000
SBC r,i Subtract with carry immediate data i from r-register
SBC r,i
r ← r - i
3 to i0 - C
110101r
1 r0 i3 i2 i1 i0 D40H to D7FH
II
7
Set if a borrow is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Subtracts the carry flag and immediate data i from the r-register.
SBC A,9 SBC MY,0DH
A register 1000 1111 1111
Memory (MY) 1110 1110 0000
C flag 0 1 0
Z flag 0 0 1