Epson S1C6200A - Page 91

S1C6200/6200A CORE CPU MANUAL EPSON 85
APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU
b) At HALT mode
c) During "PSET" instruction execution
Fig. A2.2.1 Timing chart of S1C6200A interrupt
a) During instruction execution
Fetch
Clock
Status
Instruction
PSET
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
PSET + CALL
PSET + JP
... 12.5 to 24.5 clock cycles
... 12.5 to 22.5 clock cycles
Interrupt processing:
Execute Note: (*1)
(*2)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
Status:
CALL
Fetch
System clock
CPU clock
Status
Instruction
5-clock Instrruction
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
Interrupt processing: 14 to 15 clock cycles
Execute Note: (*1)
(*2)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
Status:
HALT
Fetch
Clock
Status
Instruction
5-clock Instrruction
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
12-clock instruction
7-clock instruction
5-clock instruction
... 12.5 to 24.5 clock cycles
... 12.5 to 19.5 clock cycles
... 12.5 to 17.5 clock cycles
Interrupt processing:
Execute Note: (*1)
(*2)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
Status:
12-clock Instrruction