Page 16 Epson Research and Development
Vancouver Design Center
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
6 Technical Description
6.1 PCI Bus Support
The S1D13706 does not have on-chip PCI bus interface support. The S1D13706P00C100
uses the PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13706P00C100 is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13706 directly supports many other host
bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 11.
The PCI Bridge FPGA must be disabled using SW1-10 in order for direct host bus inter-
faces to operate properly.
6.3 S1D13706 Embedded Memory
The S1D13706 has 80K bytes of embedded SRAM. The 80K byte display buffer address
space is directly and contiguously available through the 17-bit address bus.
6.4 Software Adjustable LCD Backlight Intensity Support Using PWM
The S1D13706 provides Pulse Width Modulation output on PWMOUT. PWMOUT can be
used to control LCD panels which support PWM control of the backlight inverter. The
PWMOUT signal is provided on the buffered LCD connector (H1).
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