FOUR
TERMINAL
OPERATION
Certain units
have
been
provided
with
four
terminal
output
to
enable
the correction
of
resistive
drop
m
connecting
leads.
When
this
correction
is
not required,
the
+F/B
and
+0/P
terminals
should be
linked
together
and the
—¥/\i
and —O/P
terminals
should
be
linked
together.
When
correction
is required
the links
should
be removed.
The
load should
be
connected to
the
+0/P and
—O/P
terminals
and
the
+F/B
and —F/B
terminals
connected
through
separate
wires
to the
appropriate
ends
of the load.
It may
be
necessary
to decouple
at the
load
with
an
electrolytic
capacitor
to prevent
instability
in this
connection.
OVER-VOLTAGE
PROTECTION
On units
fitted
with
over-voltage
protection
the over-
voltage
trip
level
adjustment
is on the
front panel
of the
unit,
and the
current
limit
control
on
the back of
the unit.
To
set a given trip
level,
set the
output voltage
to this
level,
and
adjust
the
"OVERVOLTAGE"
control
until
the output
voltage
falls to a low
level.
Set
the
voltage
adjustment
controls
fully
anti-clockwise,
the
output
(or
mains)
switch
to off, and
then on. This
resets the
overvoltage
trip.
Re-adjust
the
output voltage
controls
to give
the
required
operating
voltage.
SECTION III
CIRCUIT
DESCRIPTION
The circuit
employs series regulator transistors
driven
via
emitter followers from a differential amplifier which compares the
voltage of a
zener
diode reference with a proportion of the output
voltage derived from a
resistive potential divider.
The
mains
supply
is connected via fuse Fl, SW1 and the input
selector to MT1.
The main
secondary winding supplies
a
bridge
rectifier,
reservoir
capacitor system which provides the main
unregulated D.C. line. The
positive
line is
connected via
the
series regulator transistors and SW2 to the positive output
terminal. The negative
line
is connected via fuse F2 to the
negative output terminal.
Supplies for the amphfier and
reference section
are
derived
from
the auxiliary 36 volt secondary winding, via rectifier diodes
D5 and D6 and
smoothed
by capacitor C2. The unstabilised
reference line is fed to zener diode Zl via resistor R2,
The
semi-
sta
bilised voltage
across Zl is fed to zener diode Z2 and Z4 via
R3 providing 10 volts positive and
approximately
5 volts negative
with
respect to the positive output terminal.
The voltage
across
Z2 feeds
the reference
zener diode Z3 and potential divider chain
R7, Tl , PI and P2, via Resistor
R4.
The base of VT1 and the negative
of
Z3 are connected to the
positive output terminal. R7 and Tl are connected
between
the
positive of Z3 and VT2 base via
R8. Any difference between the
voltages at VT1 and VT2 bases is
amplified at
the collector of
VT2
and
applied
to VT3 base. After further
amplification
at
VT3 collector the signal is applied
to the
emitter
followers
of the
series regulator stage in such a sense as to
oppose
the original
signal at VT1 and
VT2 bases. The action
of the loop
is therefore
to maintain zero voltage between VT1 and
VT2 bases.
i
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