Fujitsu F2MC-16LX - Page 2

Fujitsu F2MC-16LX

706 pages

Save Page as PDF

To Next Page

To Next Page

To Previous Page

To Previous Page

Loading...

Table of Contents

Default Chapter9
- Table of Contents9
Chapter 1 Overview17
- Feature of MB90330 Series18
- Block Diagram23
- Package Dimension24
- Pin Assignment26
- Pin Function27
- I/O Circuit Types34
- Handling of Device37
Chapter 2 Cpu41
- Outline Specification of CPU42
- Memory Space43
- Register of CPU48
- Prefix Code59
Chapter 3 Interrupt63
- Outline of Interrupt64
- Interrupt Cause and Interrupt Vector67
- Interrupt Control Register and Peripheral Function70
  - Interrupt Control Registers (ICR00 to ICR15)72
  - Interrupt Control Register Functions74
- Hardware Interrupt77
- Software Interrupt88
- Interrupts by Extended Intelligent I/O Service (EI 2 OS)90
  - Extended Intelligent I/O Service92
- OS) Descriptor (ISD)92
  - Each Register of Extended Intelligent I/O Service94
- OS) Descriptor (ISD)94
  - Operation of Extended Intelligent I/O Service (EI 2 OS)97
  - Procedure for Use of Extended Intelligent I/O Service (EI 2 OS)98
- OS) Processing Time99
Chapter 4 Reset129
- Outline of Reset130
- Reset Factors and Oscillation Stabilization Wait Times132
- External Reset Pin134
- Reset Operation135
- Reset Factor Bit137
- State of each Pin at Reset139
Chapter 5 Clock141
- Outline of Clock142
- Block Diagram of Clock Generation Section145
- Clock Select Register (CKSCR)148
- Clock Mode151
- Oscillation Stabilization Wait Time154
- Connection of Oscillator and External Clock155
Chapter 6 Low-Power Consumption Mode157
- Outline of Low-Power Consumption Mode158
- Block Diagram of Low-Power Consumption Control Circuit161
- Low-Power Consumption Mode Control Register (LPMCR)163
- CPU Intermittent Operation Mode166
- Standby Mode167
- State Transition Diagram176
- State of the Pin During Standby Mode, Hold, and Reset178
- Precautions When Using Low-Power Consumption Mode188
Chapter 7 Mode Setting191
- Mode Setting192
- Mode Pins (MD2 to MD0)193
- Mode Data194
- External Memory Access198
- Operation in each Mode of Mode Setting204
Chapter 8 I/O Port213
- Functions of I/O Ports214
- I/O Port Register215
Chapter 9 Timebase Timer221
- Overview of Timebase Timer222
- Configuration of Timebase Timer224
- Timebase Timer Control Register (TBTC)226
- Interrupt of Timebase Timer228
- Operations of Timebase Timer229
- Precautions When Using Timebase Timer231
- Program Example of Timebase Timer233
Chapter 10 Watchdog Timer235
- Overview of Watchdog Timer236
- Watchdog Timer Control Register (WDTC)238
- Configuration of Watchdog Timer240
- Operations of Watchdog Timer242
- Precautions When Using Watchdog Timer244
- Program Examples of Watchdog Timer245
Chapter 11 Watch Timer247
- Overview of Watch Timer248
- Configuration of Watch Timer249
- Watch Timer Control Register (WTC)250
- Operation of Watch Timer252
Chapter 12 16-Bit I/O Timer254
- Overview of 16-Bit I/O Timer254
- Register of 16-Bit I/O Timer256
- Operation of 16-Bit I/O Timer271
Chapter 13 Usb Function281
- Overview of USB Function282
- Block Diagram of USB Function283
- Register of USB Function284
- Operation Explanation of USB Function312
CHAPTER 14 USB Mini-HOST325
- Feature of USB Mini-HOST326
- Diversity with USB HOST327
- Block Diagram of USB Mini-HOST328
- Register of USB Mini-HOST329
- Operation of USB Mini-HOST352
- Each Token Flow Chart of USB Mini-HOST369
Chapter 15 Pwc Timer371
- Overview of PWC Timer372
- Register of PWC Timer374
- Movement of PWC Timer382
- Precautions When Using PWC Timer397
Chapter 16 16-Bit Reload Timer399
- Overview of 16-Bit Reload Timer400
  - Function of 16-Bit Reload Timer401
  - Block Diagram of 16-Bit Reload Timer403
- Registers of 16-Bit Reload Timer404
  - Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2)405
  - 16-Bit Timer Register 0 to 2 (TMR0 to TMR2)/ 16-Bit Reload Register 0 to 2 (TMRLR0 to TMRLR2)409
- Movement of 16-Bit Reload Timer411
Chapter 17 8/16-Bit Ppg Timer419
- Overview of 8/16-Bit PPG Timer420
  - Block Diagram of 8/16-Bit PPG Timer421
- Registers of 8/16-Bit PPG Timer423
- Operation of 8/16-Bit PPG Timer432
Chapter 18 Dtp/External Interrupt437
- Overview of Dtp/External Interrupt438
- Register of Dtp/External Interrupt439
- Operation of Dtp/External Interrupt441
- Precaution of Using Dtp/External Interrupt443
Chapter 19 8/10-Bit A/D Converter446
- Overview of 8/10-Bit A/D Converter446
- Configuration of 8/10-Bit A/D Converter447
- Register of 8/10-Bit A/D Converter449
- Explanation of Operation of 8/10-Bit A/D Converter458
  - Conversion Operation Using Μdmac or EI461
  - A/D-Converted Data Protection Function462
- Precautions When Using 8/10-Bit A/D Converter464
- Example of Program-1 of 8/10-Bit A/D Converter (Example of Starting the EI 2 os in the Single Mode)465
- Example of Program-2 of 8/10-Bit A/D Converter (Example of Starting the EI 2 os in the Continuous Mode)468
- Example of Program-3 of 8/10-Bit A/D Converter (Example of Starting the EI 2 os in the Stop Mode)471
Chapter 20 Extended I/O Serial Interface475
- Outline of Extended I/O Serial Interface476
- Register in Extended I/O Serial Interface477
- Operation of Extended I/O Serial Interface484
Chapter 21 Uart491
- Overview of UART492
- UART Block Diagram494
- UART Pins497
- Register of UART498
- UART Interrupt510
  - Receive Interrupt Generation and Flag Set Timing512
  - Transmit Interrupt Generation and Flag Set Timing514
- UART Baud Rate516
- Explanation of Operation of UART520
- Notes on Using UART533
- Example of UART Programming534
Chapter 22 I 2 C Interface537
- I 2 C Interface Outline538
- I 2 C Interface Register540
- I 2 C Interface Operation552
Chapter 23 Rom Mirror Function Selection Module559
- Overview of ROM Mirror Function Select Module560
- ROM Mirror Function Select Register (ROMM)561
Chapter 24 Address Match Detection Function563
- Overview of Address Match Detection Function564
- Block Diagram of Address Match Detection Function565
- Configuration of Address Match Detection Function566
  - Address Detection Control Register (PACSR)567
  - Detect Address Setting Registers (PADR0, PADR1)569
- Explanation of Operation of Address Match Detection Function571
  - Example of Using Address Match Detection Function572
- Program Example of Address Match Detection Function577
Chapter 25 3M-Bit Flash Memory579
- Overview of 3M-Bit Flash Memory580
- Sector Configuration of 3M-Bit Flash Memory581
- Flash Memory Control Status Register (FMCS)582
- Automatic Algorithm Initiation Method of Flash Memory585
- Check the Execution State of Automatic Algorithm586
- Write/Erase of Flash Memory593
CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING603
- Basic Configuration604
- Oscillation Clock Frequency and Serial Clock Input Frequency606
- Flash Microcomputer Programmer System Configuration607
- Example of Connecting Serial Writing608
  - Example Connection in Single-Chip Mode (When Using User Power)609
  - Example of Minimum Connection to Flash Microcomputer Programmer (When Using User Power)611
Appendix613
- Appendix A Memory Map614
- Appendix B Instruction630

Other manuals for Fujitsu F2MC-16LX

Operation Manual10 pages

Related product manuals

Fujitsu F2MC-16L

Preview: Fujitsu F2MC-16LX Series

Fujitsu F2MC-16LX Series

Fujitsu F2MC-8L Series

Fujitsu ALL Series

Preview: Fujitsu MB91460

Fujitsu MB91460

Fujitsu MB91460 SERIES

Fujitsu MB904 Series