Section 4
4-29
4.3.3.7. The Integrator.
This consists of an ultrastable Teflon capacitor C18, and a FET buffer amplifier
U15.
4.3.3.8. Charge Balance Sampler.
This consists of U16, a limit comparator, and U4, a very fast flip-flop. On the rising
edge of the master clock the output of the limit detector is sampled. If the integrator
has gone over the preset limit, then on the next falling edge of the master clock, a
charge packet is taken out of the integrator capacitor to bring it back below the
preset limit.
4.3.3.9. Master Clock.
This consists of U7, a crystal oscillator chip, U1, a 4-bit up/down counter. The
4.9152 MHz crystal and 5 or 6 counter was chosen so that exactly 2
14
master
clock cycles would occur during one power line cycle.
4.3.3.10.Conversion Timer.
This consists of U6, a 14-bit ripple counter and U8, a dual flip-flop configured as a
2-bit ripple counter. This circuit is configured so that 2
12
- 2
16
master clock cycles
would occur during one conversion, (depending on the frequency of the oscillator
chosen, and the number of power line cycles to integrate over). The timer counts the
falling edges of the master clock.
4.3.3.11.Interconversion Pause.
This consists of 1/2 of U5, a one shot, and U3, a dual flip-flop configured as a
sampler with "metastability" rejection. The one shot is fired by the falling edge of
the conversion timer output, and is sampled on the rising edges of the master clock
by U3. This gives a high degree of flexibility and simplicity to the timing circuitry.
To Next Page
Loading...