Page 13 (Data Input and PLL Clock Waveforms (IC-12))

Handic 0050 - Data Input and PLL Clock Waveforms (IC-12)

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Table of Contents

Contents2
Specifications3
Principles of Operation4
Disassembly Diagram5
Block Diagram6
General Operation Outline7
Alignment and Test Point Positions8
Alignment Preparation8
Reference Frequency OSC Alignment9
IF Section Alignment9
VCO Alignment9
RF AMP Alignment10
Overall Alignment and Sensitivity Measurement12
Zeromatic Function and How to Check It12
Data Input and PLL Clock Waveforms13
Waveforms at R0 - R13 Output Terminals of CPU (IC-1)14
O1-O7 Output Signals in Program Mode When CH1 Display 138 Mhz15
Memory Check16
Reception Check17
Clock Function Check18
Wiring Diagram19
Linear PC Board (Top View)20
Linear PC Board (Bottom View)21
Logic PC Board (Top View)22
Logic PC Board (Bottom View)23
Troubleshooting24
Integrated Circuit Lead Identification26
Diode Identification and Lead Polarity32
Semiconductor Lead Identification33
Micro-Computer (IC-1) Port Format34
Parts List35
Exploded View42
Schematic Diagram (Logic Section)44
Schematic Diagram (Linear Section)45

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