ADV7342/ADV7343
Rev. 0 | Page 19 of 88
Pin No. Mnemonic
Input/
Output Description
36 R
SET2
I
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from R
SET2
to AGND.
45, 35
COMP1,
COMP2
O Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to V
AA
.
44, 43, 42
DAC 1, DAC 2,
DAC 3
O DAC Outputs. Full and low drive capable DACs.
39, 38, 37
DAC 4, DAC 5,
DAC 6
O DAC Outputs. Low drive only capable DACs.
21 SCL/MOSI I Multifunctional Pin: I
2
C Clock Input/SPI Data Input.
20 SDA/SCLK I/O Multifunctional Pin: I
2
C Data Input/Output. Also, SPI clock input.
19
ALSB/SPI_SS
I Multifunctional Pin: This signal sets up the LSB
2
of the MPU I
2
C address. Also, SPI slave select.
46 V
REF
Optional External Voltage Reference Input for DACs or Voltage Reference Output.
41 V
AA
P Analog Power Supply (3.3 V).
10, 56 V
DD
P
Digital Power Supply (1.8 V). For dual-supply configurations, V
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
1 V
DD_IO
P Input/Output Digital Power Supply (3.3 V).
34 PV
DD
P
PLL Power Supply (1.8 V). For dual-supply configurations, PV
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
33 EXT_LF1 I External Loop Filter for On-Chip PLL 1.
31 EXT_LF2 I External Loop Filter for On-Chip PLL 2.
32 PGND G PLL Ground Pin.
40 AGND G Analog Ground Pin.
11, 57 DGND G Digital Ground Pin.
64 GND_IO G Input/Output Supply Ground Pin.
1
ED = enhanced definition = 525p and 625p.
2
LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I
2
C address to 0xD4. Setting it to 1 sets the I
2
C address to 0xD6. In the ADV7343, setting the
LSB to 0 sets the I
2
C address to 0x54. Setting it to 1 sets the I
2
C address to 0x56.
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