Hitachi 57F59A - Page 56

CH U/D, INPUT
A
DJUST MODE
VBI SLICER
▶
V CHIP
CLOCK TEST
AFC TEST
OSD POSITION
ISF MODE
I2C OPEN
MAINTENANCE
MEMORY INIT
▲▼
CH U/D, INPUT
A
DJUST MODE
VBI SLICER
V CHIP
▶ CLOCK TEST 11:43:50
AFC TEST
OSD POSITION
ISF MODE
I2C OPEN
MAINTENANCE
MEMORY INIT
▲▼
ADJUST MODE
START **
TIME OUT **
STATUS **
◀▶
DATA
Change
▲▼
CH U/D, INPUT
A
DJUST MODE
VBI SLICER
V CHIP
CLOCK TEST 11:43:50
▶
AFC TEST

OSD POSITION
ISF MODE
I2C OPEN
MAINTENANCE
MEMORY INIT
▲▼
▲▼
EXIT
Select or
▶
CH U/D, INPUT
A
DJUST MODE
VBI SLICER
V CHIP
CLOCK TEST 11:43:50
AFC TEST
▶ OSD POSITION
ISF MODE
I2C OPEN
MAINTENANCE
MEMORY INIT
A
DJUST MODE
VBI SLICER
V CHIP
CLOCK TEST 11:43:50
▶ AFC TEST
5
OSD POSITION
ISF MODE
I2C OPEN
MAINTENANCE
MEMORY INIT
EXIT
Select or
▶
VPOSI
**
CLK1 **
HPOSI1 **
CLK2 **
HPOSI2 **
CLK3 **
HPOSI3 **
EXIT
Select or
▶
◀▶
DATA
Chan
g
e
2.16 Adjustment OSD Flowchart (Cont.)
DP65
55
DP55