Hitachi AP1 - Page 120

HMCS47C,HMCS47CL----------------------------------------------------------
I (PagePartl~
Bank Part
I\~ Page Part~ r--- Address Part
Figure 4 ROM Addressing for Pattern Generation
Table 2 Bank Part Truth Table of Pattern Gener"tion
PC ..
P2
1 (Bank 1)
1
0
o (Bank 0)
1
0
Bank part of ROM address
to be referenced to
1 (Bank 1)
1 (Bank 1)
1 (Bank 1)
o (Bank 0)
Pattern
of ROM
Loaded into the accumulator
and B register
Figure 5 Correspondence of Each Bit of Pattern
Table 3 Example of Pattern Instructions
Before Execution
Referred
ROM
ROM
After Execution
PC
p
C B
A
Address
Bank
00-3F
1
0 A
0
Bank 010-20
(0-3F)
(10-20)
Bank 00-3F
7
1
4
0
Bank 1 29-00
(0-3F)
(61-00)
Bank 1 30-00
4 0/1**
0
9
Bank 1
30-09
(62-00)
(62-09)
Bank 1 30-00
1
0/1**
F
9
Bank 1 31-39
(62-00)
(63-39)
• "-" means that the value does not change after execution of the instruction.
"0/1" means that either "0" or "1" may be selected.
118
Pattern
B A
R2
120
2
B
-
220
- -
4
320
2
B
4
223
-
-
4
R3
*
-
B
B
C