Hitachi H8S/2199 - User Manual

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Hitachi Single-Chip Microcomputer

H8S/2199 Series

H8S/2199

HD6432199

H8S/2198

HD6432198

H8S/2197

HD6432197

H8S/2196

HD6432196

H8S/2199F-ZTAT

™

HD64F2199

Hardware Manual

ADE-602-191

Rev 1.0

2/15/00

Hitachi, Ltd.

Table of Contents

Default Chapter3
- Table of Contents3
- Overview21
Section 1 Overview22
- Overview22
- Internal Block Diagram28
- Pin Arrangement and Functions29
  - Pin Arrangement29
  - Pin Functions30
Cpu37
- Overview37
- CPU Operating Modes40
- Address Space45
- Register Configuration46
- Data Formats50
  - General Register Data Formats50
  - Memory Data Formats52
- Instruction Set53
- Addressing Modes and Effective Address Calculation67
  - Addressing Mode67
  - Effective Address Calculation70
- Processing States74
- Basic Timing79
  - On-Chip Memory (ROM, RAM)79
  - On-Chip Supporting Module Access Timing80
MCU Operating Modes81
- Overview81
  - Operating Mode Selection81
  - Register Configuration81
- Register Descriptions82
  - Mode Control Register (MDCR)82
  - System Control Register (SYSCR)82
- Operating Mode (Mode 1)83
- Address Map in each Operating Mode84
Power-Down State86
- Overview86
- Medium-Speed Mode97
- Sleep Mode98
  - Clearing Sleep Mode98
- Module Stop Mode99
- Standby Mode100
  - Clearing Standby Mode100
  - Setting Oscillation Settling Time after Clearing Standby Mode100
- Watch Mode102
  - Clearing Watch Mode102
- Subsleep Mode103
  - Clearing Subsleep Mode103
- Subactive Mode104
  - Clearing Subactive Mode104
- Direct Transition105
  - Overview of Direct Transition105
Exception Handling106
- Overview106
- Reset109
- Interrupts111
- Trap Instruction112
- Stack Status after Exception Handling113
- Notes on Use of the Stack114
Section 6 Interrupt Controller115
- Overview115
- Interrupt Sources124
- Interrupt Operation129
- Usage Notes138
Rom140
- Overview140
  - Block Diagram140
- Overview of Flash Memory141
- Flash Memory Register Descriptions148
- On-Board Programming Modes157
  - Boot Mode158
  - User Program Mode163
- Programming/Erasing Flash Memory164
- Flash Memory Protection170
- Interrupt Handling When Programming/Erasing Flash Memory173
- Flash Memory Writer Mode174
- Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions186
Ram187
- Overview187
  - Block Diagram187
Clock Pulse Generator188
- Overview188
  - Block Diagram188
  - Register Configuration188
- Register Descriptions189
  - Standby Control Register (SBYCR)189
  - Low-Power Control Register (LPWRCR)190
- Oscillator191
  - Connecting a Crystal Resonator191
  - External Clock Input193
- Duty Adjustment Circuit196
- Medium-Speed Clock Divider196
- Bus Master Clock Selection Circuit196
- Subclock Oscillator Circuit197
  - Connecting 32.768 Khz Crystal Resonator197
  - When Subclock Is Not Needed198
- Subclock Waveform Shaping Circuit198
- Notes on the Resonator198
Section 10 I/O Port199
- Overview199
- Port 0203
- Port 1206
  - Overview206
- Port 2206
  - Register Configuration206
  - Pin Functions210
- Port 3212
- Port 4218
- Port 6232
- Port 7242
- Port 8251
Section 11 Timer a261
- Overview261
- Register Descriptions263
- Operation266
Section 12 Timer B267
- Overview267
- Operation274
Section 13 Timer J275
- Overview275
- Operation288
Section 14 Timer L293
- Overview293
- Register Descriptions296
- Operation300
  - Compare Match Clear Operation300
Section 15 Timer R302
- Overview302
- Register Descriptions305
- Operation316
- Interrupt Cause321
- Settings for Respective Functions322
Section 16 Timer X1326
- Overview326
- Register Descriptions330
- Operation346
- Operation Mode of Timer X1352
- Interrupt Causes353
- Exemplary Uses of Timer X1354
- Precautions When Using Timer X1355
Section 17 Watchdog Timer (WDT)360
- Overview360
- Register Descriptions363
- Operation368
- Interrupts371
- Usage Notes371
Section 18 8-Bit PWM373
- Overview373
- Register Descriptions375
- 8-Bit PWM Operation379
Section 19 12-Bit PWM380
- Overview380
- Register Descriptions383
  - 12-Bit PWM Control Registers (CPWCR, DPWCR)383
  - 12-Bit PWM Data Registers (DPWDR, CPWDR)386
- Operation387
  - Output Waveform387
Section 20 14-Bit PWM389
- Overview389
- Register Descriptions392
- 14-Bit PWM Operation395
Section 21 Prescalar Unit396
- Overview396
- Registers399
- Noise Cancel Circuit403
- Operation403
Section 22 Serial Communication Interface 1 (SCI1)406
- Overview406
- Register Descriptions410
- Operation431
- SCI Interrupts459
- Usage Notes460
Section 23 I C Bus Interface (IIC)467
- Overview467
- Register Descriptions471
- Operation497
- Usage Notes517
Section 24 A/D Converter521
- Overview521
- Register Descriptions525
- Interface to Bus Master534
- Operation535
  - Software-Triggered A/D Conversion535
  - Hardware- or External-Triggered A/D Conversion536
- Interrupt Sources537
Section 25 Address Trap Controller (ATC)538
- Overview538
- Register Descriptions539
  - Address Trap Control Register (ATCR)539
  - Trap Address Register 2 to 0 (TAR2 to TAR0)541
- Precautions in Usage542
Section 26 Servo Circuits561
- Overview561
  - Functions561
  - Block Diagram563
- Servo Port563
- Reference Signal Generators572
- HSW (Head-Switch) Timing Generator595
- High-Speed Switching Circuit for Four-Head Special Playback620
- Drum Speed Error Detector624
- Drum Phase Error Detector635
- Capstan Speed Error Detector644
- Capstan Phase Error Detector654
- X-Value and Tracking Adjustment Circuit662
- Digital Filters667
- Additional V Signal Generator684
- CTL Circuit690
- Sync Signal Detector739
- Servo Interrupt754
Section 27 Sync Separator for OSD and Data Slicer762
- Overview762
- Register Description766
- Operation789
Section 28 Data Slicer803
- Overview803
- Register Description807
- Operation818
  - Slice Line Specification818
  - Slice Sequence821
Section 29 On-Screen Display (OSD)822
- Overview822
- Description of Display Functions827
- Settings in Character Units830
- Settings in Row Units841
- Settings in Screen Units848
- Other Settings858
- Digital Output863
- Notes on OSD Font Creation871
- OSD Oscillator, AFC, and Dot Clock875
- OSD Operation in CPU Operation Modes878
- Character Data ROM (OSDROM) Access by CPU879
  - Serial Timer Control Register (STCR)879
Section 30 Electrical Characteristics880
- Absolute Maximum Ratings880
- Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196881
- Electrical Characteristics of HD64F2199903
Appendix A Instruction Set925
- Instructions925
- Instruction Codes936
- Operation Code Map946
- Number of Execution States950
- Bus Status During Instruction Execution960
- Change of Condition Codes974
Appendix B Internal I/O Registers979
- Addresses979
- Function List988
- Bus Interface1070

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Hitachi H8S/2199 Specifications

General

Brand	Hitachi
Model	H8S/2199
Category	Computer Hardware
Language	English

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