----------------------------------LCD-III
13. The voltage
that
drops
between
the
power supply terminals
(Vee.
VI.
V2.
V,)
and
each common
or
segment
output
terminal.
14. The supply current
at
Vee·
VOH·
2.3V in
"Halt"
state. in
the
c
..
that
the
crystal oscillation for timer
is
not selected.
Current
that
flows in
the
input/output
circuit end in
the
power supply circuit
for
LCD
is
excluded.
16. Interrupt inputs
must
be
retained for
two
or
more instruction cycle time
at
both
"High" and
"Low"
levels.
INTo.INT
I
• SIGNAL DESCRIPTION
The input and output signals for the LCD-III shown in PIN
ARRANGEMENT are described in the following paragraphs.
• VCCandGND
Power is supplied
to
the LCD-III using these two pins.
Vee
is power and
GND
is the ground connection.
• RESET
This pin allows resetting
of
the LCD-III at times other
than the automatic resetting capability
(ACL; Built·in Reset
Circuit) already in the
LCD·III. The LCD·III can be reset
by pulling
RESET High.
Refer
to
RESET FUNCTION for additional infonnation.
•
OSC
I
and
OSC
2
These pins provide control input for the on-chip clock
oscillator circuit. A resistor, a ceramic
ftlter circuit,
or
an
external oscillator
can
be connected
to
these pins
to
provide a
system
clock with various degrees
of
stability/cost tradeoffs.
Lead length and stray capacitance on these two pins should be
minimized.
Refer
to
OSCILLATOR for recommendations about these
pins.
• HIT
This pin
is
used
to
place the LCD-III in the HALT state
(Stand-by Mode). The LCD·III
can
be moved into the halt
state
by
pulling
HLT
Low.
In the halt state the internal clock stops and all the internal
status (RAM, Registers,
Carry, Status, Program Counter, and
all the internal statuses) are maintained.
Consequently power
consumption is greatly reduced. By pulling
m:r
high, the
LCD-Ill starts operation from the status just before the halt
state.
Refer
to
HALT FUNCTION for details
of
halt mode.
• TEST
This pin is
not
for user application and must be connected
toVec·
•
INTo
and
INTI
These pins provide the capability for asynchronously apply·
ing an external interrupt
to
the LCD·III.
Refer
to
INTERRUPTS for additional information.
1-----tINT---iJ
•
VI,
V2
andV3
Power for liquid crystal display
are
supplied
to
the LCD·III
using these pins (VCC
~
VI
~
V
2
~
V3
~
GND).
•
Roo
to
R03
These four lines are a 4-bit input channel.
Refer to
INPUT/OUTPUT for additional infonnation.
•
RIO
to
R13,
R20
to
R23
These 8 lines
are
arranged into two 4·bit Input/Output
common channels.
4·bit registers (data I/O register)
are
attached
to
these chan·
nels. Each channel
is
directly addressed by the operand
of
an
instruction.
I/O configuration
of
each pin can be specified
among Open Drain, With
Pull Up
MOS,
and
CMOS
using a mask
option.
Refer
to
INPUT/OUTPUT for additional infonnation.
•
R30
to
R33
These four lines are a 4·bit
output
channel.
4·bit register
is
attached
to
this channel. This channel is
directly addressed by the operand
of
an instruction. I/O con·
figuration
of
each pin can be specified among Open Drain and
CMOS
using a mask option.
Refer
to
INPUT/OUTPUT for additional infonnation.
•
Do
to
013
These are 14 discrete signals which can be configured
as
Input/Output lines.
Refer
to
INPUT/OUTPUT for additional infonnation.
• DI4/X0,DI5/X1
DI4/XO and
DIS
/XI require a mask option in the follow·
ing 3 types.
• Discrete I/O (common terminal)
• Crystal circuit connecting terminals (with internal halt)
• Crystal circuit connecting terminals (no internal halt)
Refer
to
INPUT/OUTPUT for additional infonnation.
• COMI
to
COM.
These pins are common tenninals for
liqUid
crystal display.
Refer to
LIQUID CRYSTAL DISPLAY for additional
in-
fonnation.
• SEGI
to
SEG32
These pins are segment tenninals for liquid crystal display.
147
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