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Hitachi AP1 - Page 207

Hitachi AP1
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--------------------------------
LCD-IV
• Liquid Crystal Display Mode Setting RegisteR
For
selection
of
the
liquid crystal display mode, data I/O registers
of
R4,
RS
and
R6 are used.
Table 9
Function
of
Liquid Crystal Display Mode Setting Registers
R41
R40
Function
0 0
Static
Selection
of
liquid crystal
O·
1
1/2
duty
display
duty
factor
(R
40
, R
41
)
1 0
1/3
duty
1
1
1/4
duty
Designation of with
or
without
R42
Function
liquid crystal segment
output
0
To
be extended
(Outputs
display
data
from Channel R
1)
extension (R
42
)
1
Not
to
be extended (Channel
R1
becomes an ordinary 4-bit
data
I/O.)
R60
Function
Liquid crystal display blanking 0
Outputs
RAM
data
for liquid crystal display
as
segment signals.
signal
(R
60
)
Segment
signals become non-selection status (blanking) regardless of
RAM
1
data
for liquid crystal display.
RAM
designation for liquid
RSI
Rso
Function
crystal display (R
so
, R
S1
)
Function varies with
liquid crystal display
duty
factor.
R63
R62
R61
R60
Function
Selection of
--------
0
0
-----
Do
not
set
in
this state.
halt function
and oscillation
~
0
1
~
With crystal for timer, with internal halt, XI, XO
circuit for
~
1
0
-----
Without crystal for timer, 0
14
and
DIS
are general I/O.
timer
----
1 1
----
With crystal for timer,
without
internal halt, XI,
XO.
I/O state
0
~
~
----
Enable:
at
halt
1
~
~
~
Disable:
(NOTE) Liquid crystal display
mode
at
resetting.
Since all bits
of
registers R4, R5
and
RS
are
set
to
"1"
by
the
reset
function,
display
mode
after
resetting becomes as
shown
below:
Liquid crystal display
duty
factor:
1/4
duty
(R.
o
=
"1",
R
..
=
"1")
Liquid crystal
segment
output
extension:
Not
extended
(R.
2
=
"1")
Designation
of
liquid crystal display blanking: Display blanking (R
60
=
"1")
Designation
of
RAM
for
liquid crystal display: Varies
correspond
to
each liquid crystal display
duty
factor.
(R
so
=
"1",
RSI
=
"1")
Designation
of
crystal
for
timer
and
internal halt: With crystal
for
timer,
without
internal
halt
(R.
I
=
"1",
R'
2
=
"1"1.
I/O
state
at
halt:
I/O
state
at
halt
becomes
disable (R
u
=
"1"1.
205